Epitaxial silicon wafers for power MOS transistors, for instance, are required to have extremely low substrate resistivity. In order to sufficiently lower the substrate resistivity of silicon wafers, it is known to dope molten silicon with an n-type dopant for resistivity adjustment (e.g. arsenic (As) and antimony (Sb)) during a pull-up step (i.e. in growing silicon crystal) of a single crystal ingot for providing silicon wafers (referred to as a single crystal ingot hereinafter). However, since such dopants are extremely volatile, it is difficult to sufficiently increase the dopant concentration in the silicon crystals. Thus, silicon wafers exhibiting desired sufficiently low resistivity is difficult to be manufactured.
Accordingly, silicon wafers with extremely low substrate resistivity have come to be used in which phosphorus (P) as an n-type dopant, which is less volatile than arsenic (As) and antimony (Sb), is doped at a high concentration (see, for instance, Patent Literatures 1 and 2).
Patent Literatures 1 and 2 disclose that, when an epitaxial film is grown on a silicon wafer having been densely doped with phosphorus, a number of stacking faults (abbreviated as “SF” hereinafter) are generated on the epitaxial film, the SF appearing on the surface of the silicon wafer in a form of steps to significantly deteriorate LPD (Light Point Defect) level on the surface of the silicon wafer. The reasons for the generation of SF are speculated as follows.
The silicon wafer having been doped with phosphorus is first heated, which results in formation of clusters (micro-precipitates) of oxygen and phosphorus. Subsequently, the silicon wafer is subjected to a heat treatment in a hydrogen gas atmosphere (hereinafter referred to as “hydrogen baking”) in order to remove a natural oxide film present on the surface of the silicon wafer. The clusters are preferentially etched to provide micropits by an etching effect of the hydrogen gas due to a difference in an etching rate between the outermost layer of the silicon wafer and the clusters. It is speculated that, when the silicon wafer provided with the micropits is subjected to an epitaxial growth, SF originating from the micropits are generated in the epitaxial film.
Accordingly, Patent Literature 1, which focuses on a correlation between the solidification rate and thermal hysteresis of a single crystal ingot and generation of SF, discloses a manufacturing method in which the generation of SF is restrained by regulating a period of time when the temperature of the single crystal ingot is in a range of 570±70 degrees C. during the pull-up step.
Further, Patent Literature 2 discloses a manufacturing method in which the generation of SF is restrained by subjecting, prior to the formation of an epitaxial film, a silicon wafer to a heat treatment in an argon gas atmosphere (hereinafter referred to as “subjected to an argon-annealing treatment”) to make the clusters on the outer layer into a solid solution.